A digital signal processor (DSP) is a special purpose computer that is designed to optimize performance for digital signal processing applications such as, for examples, fast Fourier transforms, digital filtering, image processing and speech recognition. Digital signal processing applications typically are characterized by real time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processing applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Thus, designs of digital signal processors may be quite different from those of general purpose computers.
A typical digital signal processor includes at least one memory for storing digital signal processing operations instructions as well as operands used in the digital signal processing operations, and a core processor, connected to the memory, for carrying out such operations. A digital signal processor also typically includes a peripheral input/output (I/O) device enabling communication with, and the transfer of data to/from, other processors and/or external devices. The core processor includes some type of computation unit for performing the digital signal processing operations (i.e., computations) on the operands based on the instructions. Many different computational schemes as well as data storage and transferring schemes have been developed for optimizing speed, accuracy, size and performance of digital signal processors.
A digital signal processor commonly operates based upon receipt of a single input clock. From this single input clock are derived a core processor clock, on which the core processor operates, and an I/O clock, on which the I/O device operates. It is not uncommon for the input clock and the I/O clock to be maintained at the same frequency.
The core processor clock may be a multiple of this input clock such that the core processor operates at a different (typically greater) clock frequency than that of the I/O device. The speed of the I/O device is limited by the speed of the external signals upon which they operate. The speed of such external signals may be limited by physical constraints and capacitances and inductances of external devices and buses. The core processor is not so limited. Therefore, it is preferable to have the core processor operate at a different, and more optimal clock frequency.
Some digital signal processors allow the user to select a ratio (e.g., X2, X2.5, X3, X3.5, X4 . . .) by which the input clock will be multiplied to produce the core processor clock. This enables the user to select, within a limited range, a core processor frequency that is best for the particular processor.
As the geometries of processors shrink, internal speed paths improve, enabling faster operation. For a particular processor, therefore, there is an optimal speed at which the processor can operate. A limitation in currently available processors is that the core processor frequency is limited by the input clock and the user-selectable core clock ratios available.
In a digital signal processing system, a cluster (i.e., four, six or eight) of processors may be interconnected by an external bus system. A host computer, connected to each of the processors in the system through the bus system, may access any of the processors. The host computer operates at a host clock frequency that may be unrelated (asynchronously related) to the input clock frequency (I/O clock frequency) of each of the processors in the cluster.
When the host wishes to access any of the processors, either the host clock and the processor I/O clock must be synchronized, or asynchronous access must be enabled. Synchronization would require some type of external synchronizing interface between the host and each processor in the cluster. Alternatively, the provision of asynchronous access would require an additional, asynchronous processor I/O interface. To date, each of the approaches aimed at enabling an asynchronously operating host to access a processor requires complex and expensive circuitry. In addition, each of such approaches may be difficult for a user to implement and use.
It is a general object of the present invention to provide an improved processor clocking scheme.